A 112Gb/s PAM4 Retimer Transceiver with Jitter-Filtering Clocking Scheme and BER Optimization Scoring 252fs_rms Clock Jitter and 10^-12 BER

This paper presents a 112Gb/s PAM4 ADC-DSP-based retimer transceiver for reaching-distance extension. An injection-locked oscillator-based jitter-filtering clocking scheme with relaxed speed limitation and low-power consumption is proposed to obtain synchronous low-jitter clocks. An internal FFE cascaded with a forward-coupling pad driver and a timing optimized 4:1 MUX are developed to mitigate the output inter-symbol interference jitter and serialization jitter, respectively. A broadband Butterworth matching network, enhanced 8-bit quantization, and high-resolution digital FFE/DFE are combined to further optimize the bit-error rate (BER). Fabricated in a 28nm CMOS process, the prototype transceiver achieves $10^{-12}$ raw BER at $112 \mathrm{~Gb} / \mathrm{s}$ while compensating 31.2 dB channel loss. The clock network delivers a lowest recovered clock jitter of $252 \mathrm{fs}_{\text {rms }}$ and best power efficiency of $0.56 \mathrm{pJ} / \mathrm{bit}$.