Activity and variability resilient in-situ timing monitoring for complex ultra-low voltage digital ICs

In-situ timing monitoring significantly enhances energy efficiency by eliminating excessive timing margins inserted in conventional digital flows to address the high sensitivity to PVT variations. However, detection reliability remains a challenge. The proposed error prediction mechanism (EP) targets robustness against miss detection due to inactive paths and guarantees production yield ($4 \sigma$) through statistical critical path identification. Automatically inserted in a $28-\mathrm{nm}$ CMOS RISC-V core microprocessor, the proposed EP recovers $86 \%$ of conventional energy margins while boosting resilience against activity masking, achieving a $61 \%$ improvement over traditional replica techniques. With minimal area (1.6%) and power overhead (2%), our EP simplifies automatic integration and overcomes reliability issues.