A 4.3 GHz Digital-Sampling PLL with Noise-Shaping SAR ADC Phase Detector

A digital-sampling PLL based on a noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) breaks the quantization noise limitation of prior ADC based PDs and enables a lower resolution ADC quantizer and CDAC to be used. Additionally, this improved ADC resolution reduces the PD gain requirement and improves the lock performance. The $2^{\text {nd }}$-order noise-shaping of the NS-SAR ADC improves the time-to-voltage resolution of the phase detector by reducing in-band quantization noise and ADC input-referred noise (e.g. comparator noise). Measurements verify that noise shaping reduces the in-band noise by about 7 dB. The 28 nm CMOS prototype operates at 4.3 GHz and consumes 13.7 mW. The measured RMS integrated jitter from 1 kHz to 100 MHz is 133 fs.