DESYNCHORNIZATION METHOD FOR SELF-TIMED CIRCUITS SYNTHESIS

The paper covers a desynchronization method that allows automating one of the stages of synthesis of a self-timed circuit based on its original synchronous behavioral description in the Verilog language.

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Publication Details

Published
2024-10-20
DOI
https://doi.org/10.29003/m4291.mmmsec-2024/170-173
Primary Topic
VLSI and FPGA Design Techniques
Type
article
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article

DESYNCHORNIZATION METHOD FOR SELF-TIMED CIRCUITS SYNTHESIS

G. A. Orlov, Dmitriy Khilko, Artem A. Grigoriev, Georgiy Appolonov
VLSI and FPGA Design Techniques
article

DESYNCHORNIZATION METHOD FOR SELF-TIMED CIRCUITS SYNTHESIS

G. A. Orlov, Dmitriy Khilko, Artem A. Grigoriev, Georgiy Appolonov
article en

Abstract

The paper covers a desynchronization method that allows automating one of the stages of synthesis of a self-timed circuit based on its original synchronous behavioral description in the Verilog language.

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DESYNCHORNIZATION METHOD FOR SELF-TIMED CIRCUITS SYNTHESIS — G. A. Orlov, Dmitriy Khilko, et al. · (2024) | TGRS Research Map | TGRS