Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses

In this article, transmission line pulse (TLP) and very fast TLP (VF-TP) systems were utilized to characterize the electrical safe operating areas (SOAs) and latent damage of silicon carbide (SiC) low-voltage nMOS devices to investigate their electrostatic discharge (ESD)-related reliability performance. The gate oxide breakdown voltages of SiC nMOS with varying gate oxide thickness were measured by dc, TLP, and VF-TLP. The TLP and VF-TLP waveforms at breakdown points were also presented and discussed. ESD capability of SiC nMOS devices with gate lengths varying from 1 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu $ </tex-math></inline-formula>m was also characterized by TLP and VF-TLP. Their ESD behaviors and failure mechanisms were discussed. Scanning electron microscopy (SEM) and technology computer-aided design (TCAD) simulations were also carried out to understand the failure mechanism. At last, the ESD-induced latent damage on SiC nMOS was characterized. A decrease in threshold voltage and an increase in drain leakage current were observed with the increase in stress cycles. The latent damage is mainly due to the gate oxide injected carriers during the avalanche operation and can be recovered after 200 °C anneal.