A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device

Artificial intelligence (AI) edge devices increasingly require the enhanced accuracy of floating-point (FP) multiply-and-accumulate (MAC) operations as well as nonvolatile on-chip memory to minimize the movement of weight data in power-off mode. Designing non-volatile compute-in-memory (nvCIM) macros for FP operations imposes several challenges, including: 1) a tradeoff between inference accuracy and weight bit-width following pre-alignment; 2) long computing latency and high energy consumption; 3) large cell array current during computation; and 4) high multi-bit readout energy consumption. In this study, we devised four schemes to address these issues, including: 1) a kernel-wise weight pre-alignment (K-WPA); 2) a rescheduled multi-bit input compression (RS-MIC); 3) HRS-favored dual-sign-bit (HF-DSB); and 4) residue-shared analog-to-digital converter (RS-ADC). A 16 Mb resistive random access memory (ReRAM) nvCIM macro fabricated for FP operations using foundry-provided ReRAM (22 nm CMOS technology) achieved an efficiency of 34.2 TFLOPS/W under BF16-input, BF16-weight, and FP32-output and 31.4 TFLOPS/W under FP16-input, FP16-weight, and FP32-output.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2024-10-22
DOI
https://doi.org/10.1109/jssc.2024.3470211
Citations
13
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
2.71
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article

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device

Ren-Shuo Liu, Hung-Hsi Hsu, Meng‐Fan Chang, Chung‐Chuan Lo et al.
13 citations
IEEE Journal of Solid-State Circuits
Advanced Memory and Neural Computing
2.71
article

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device

Ren-Shuo Liu, Hung-Hsi Hsu, Meng‐Fan Chang, Chung‐Chuan Lo, Ashwin Sanjay Lele, Kea‐Tiong Tang, Wei-Hsing Huang, Chih-Cheng Hsieh, Shih-Hsin Teng, Wei‐Ting Hsu, Chung-Cheng Chou, Ping-Sheng Wu, Win-San Khwa, Tai-Hao Wen, Bo Zhang, Yu‐Chen Chang, Hua-Jin Wen, Zhao-En Ke, Yu-Der Chih, Yu-Hsiang Chin, Tsung-Yung Jonathan Chang
article en
13 citations

Abstract

Artificial intelligence (AI) edge devices increasingly require the enhanced accuracy of floating-point (FP) multiply-and-accumulate (MAC) operations as well as nonvolatile on-chip memory to minimize the movement of weight data in power-off mode. Designing non-volatile compute-in-memory (nvCIM) macros for FP operations imposes several challenges, including: 1) a tradeoff between inference accuracy and weight bit-width following pre-alignment; 2) long computing latency and high energy consumption; 3) large cell array current during computation; and 4) high multi-bit readout energy consumption. In this study, we devised four schemes to address these issues, including: 1) a kernel-wise weight pre-alignment (K-WPA); 2) a rescheduled multi-bit input compression (RS-MIC); 3) HRS-favored dual-sign-bit (HF-DSB); and 4) residue-shared analog-to-digital converter (RS-ADC). A 16 Mb resistive random access memory (ReRAM) nvCIM macro fabricated for FP operations using foundry-provided ReRAM (22 nm CMOS technology) achieved an efficiency of 34.2 TFLOPS/W under BF16-input, BF16-weight, and FP32-output and 31.4 TFLOPS/W under FP16-input, FP16-weight, and FP32-output.

IEEE Journal of Solid-State CircuitsVol. 60(1)
Georgia Institute of Technology (US), Taiwan Semiconductor Manufacturing Company (United States) (US), National Tsing Hua University (TW), Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Affordable and clean energy
Openalex Percentile: Top 9%
Advanced Memory and Neural Computing
2.71
DOISourceOpenAlex
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