Analysis of etched drain based <scp>Cylindrical agate‐all‐around tunnel field effect transistor</scp> based static random access memory cell design

Abstract This paper aims to propose a novel method for designing an static random access memory (SRAM) cell using an etched drain based Cyl GAA TFET with a hetero‐substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing static noise margin (SNM) as well as N‐curve methods. With respect to the 16 nm MOSFET based SRAM cell, the proposed device‐based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in static voltage noise margin (SVNM), an 8.623% increase in static current noise margin (SINM), an 8.152% increase in write trip voltage (WTV), a 12.86% increase in write trip current (WTI), a 27.62% increase in static power noise margin (SPNM), and a 19.95% increase in write trip power (WTP). The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems.