Enhancing Reliability in Multilevel Inverter: A Fault‐Tolerant Approach With Reduced Switch Count

ABSTRACT Reliability is a major concern in multilevel inverters (MLI) due to the increased number of power switches and diodes, which increases the chance of switch failures and complicates the inverter design. The primary challenges faced by the current MLI design include higher control complexity, increased parasitic elements, more extensive protection, and lack of multiple fault tolerance. Therefore, developing reduced switch MLI with fault‐tolerant ability is crucial to ensure system availability and prevent adverse outcomes. To address these challenges, this article introduces a highly resilient fault‐tolerant reduced switch count (FTRSC) MLI topology offering fault tolerance with minimal switch count. The proposed topology provides fault tolerance in case of single‐ and multiple‐switch open‐circuit (OC) failures. The inherent fault‐tolerant operation is analyzed for the proposed topology's symmetric and asymmetric configurations. The simulation and experimental results validate the effectiveness of the proposed topology considering normal, faulty, and postfault conditions. Furthermore, the reliability evaluation of the proposed work is carried out using the Markov chain model, resulting in a high total mean time to failure of approximately 117,550 h/failures, along with an efficiency of 96.3%. These findings demonstrate that the proposed circuit has enhanced reliability and extended mean time to failure, affirming its suitability for sensitive industrial applications. Finally, a thorough comparison with recent studies highlights the superiority of the proposed system.