VLFF — A very low-power flip-flop with only two clock transistors

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively. • This paper proposed a very low-power flip-flop with only two single-phase clock transistors. • Proposed flip-flop is the most power-efficient amongst all considered. state-of-the-art flip-flops for data activities in the range of 0 – 45%. • Test-chip implemented in TSMC 65nm GP PDK validates the power savings of the proposed flip-flop over 18TSPC, and TGFF.