Circuitry Methods for Compensating Parasitic Capacitances of SiGe and CMOS SOI Transistors in High-Temperature Operational Amplifiers

High-temperature technologies for the production of analog microcircuits, including SiGe and SOI, impose a number of restrictions on the numerical values of the capacitance’s transistors used and, as a consequence, the operating frequency range of devices this class. The article discusses circuitry methods that provide for CMOS and BJT transistors an electronic circuit to minimize the influence of parasitic capacitances on the high-frequency cutoff of the voltage gain operational amplifiers and the frequency dependence of the common mode rejection ratio of input differential stages. As an example, the results of simulation in the Cadence environment of CMOS operational amplifiers using XB06 and TSMC processes transistor models are presented to show the effectiveness of the proposed circuit solutions.