Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress

This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{T})$ </tex-math></inline-formula> shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.