A <i>D</i>-Band High-Gain Low-Noise Amplifier With Transformer-Embedded Network <i>G</i> _max-Core in 40-nm CMOS

A D-band high-gain low-noise amplifier (LNA) utilizing novel transformer-based four-stage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\max }$ </tex-math></inline-formula>-cores in a 40-nm bulk CMOS process is proposed in this letter. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\max }$ </tex-math></inline-formula> -core is constructed by a Y-embedded network using a transformer, which separates the gate and drain bias. This approach solved the limitations in the traditional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\max }$ </tex-math></inline-formula>-core structure which the gate and drain bias are constrained to the same voltage. The power consumption is reduced and gain is improved, while achieving a lower noise figure (NF). A 27.74-dB peak gain is measured at 143.5 GHz, with a 3-dB bandwidth of 7 GHz, and the minimum NF is 7.6 dB. The fabricated chip occupies an area of 0.35 mm2 with all pads and the dc power consumption is 27.1 mW.