Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

Abstract Ternary adders have produced more benefits compared to binary adders i.e., the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32 nm. At 32 nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. Carbon Nano-tube Field Effect Transistors (CNFETs) are one of the technologies to work efficiently when the channel length is 32 nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances energy efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as Gate Diffusion Input (GDI) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the Power Delay product (PDP) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.