Plateau Voltage and Dynamic Capacitance Effect on SiC MOSFETs’ Gate Ringing

Gate ringing of power MOSFETs is one of the factors that limits the switching frequency and the ruggedness of silicon carbide (SiC) MOSFETs. However, the origin and cause mechanism of the gate ringing depending on the operating current and the temperature have not been yet clear. This article discusses the gate ringing behavior under different operating conditions for the first time and examines the fundamental causes of the differences. Through double pulse test and five-contact mixed-mode simulations, it was confirmed that gate ringing becomes more severe at higher currents and weaker at higher temperatures. This can be attributed to the variation in plateau voltage under different operating conditions, which affects the switching speed of the device. Consequently, this indicates a difference in source current rating (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {dI}_{\text {S}}$ </tex-math></inline-formula>/dt), leading to variations in gate ringing. In addition, the influence of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GD}}$ </tex-math></inline-formula> as a damper on gate ringing was compared, as it could cause differences in gate ringing. However, it was confirmed that, in practice, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {GD}}$ </tex-math></inline-formula> does not dominantly influence the variations in gate ringing behavior with respect to operating current and temperature.