Fully Parallel, One-Cycle Random Shuffling for Efficient Countermeasure Against Side Channel Attack and Its Complexity Verification

Hiding countermeasures are the most widely utilized techniques for thwarting side-channel attacks. Commonly, the Fisher-Yates algorithm is adopted in hiding countermeasures with permuted operation for its security and efficiency in implementation, yet the inherently sequential nature of the algorithm imposes limitations on hardware acceleration. In this work, we propose a novel method named Addition Round Rotation (<inline-formula><tex-math notation="LaTeX">$\mathsf {ARR}$</tex-math></inline-formula>), which can introduce a time-area trade-off with block-based permutation. Our findings indicate that this approach can achieve a permutation brute force complexity level ranging from <inline-formula><tex-math notation="LaTeX">$2^{128}$</tex-math></inline-formula>, with the modified version achieving up to <inline-formula><tex-math notation="LaTeX">$2^{288}$</tex-math></inline-formula> in a single clock cycle, while maintaining substantial resistance against second-order analysis. To substantiate the security of our proposed method, we introduce a new validation technique – <i>Identity Verification</i>. This technique allows theoretical validation of the proposed algorithm’s security and is consistent with the experimental results. Finally, we introduce an actual hardware design and provide the implementation results on Application-Specific Integrated Circuit (ASIC). The measured performance demonstrates that our proposal fully supports the practical applicability.