CLEAR Cross-Layer Resilience: A Retrospective
Editor’s notes: This article presents an overview of the Cross-Layer Exploration for Architecting Resilience (CLEAR) framework, highlighting the historical context behind its development, key insights gained from its application, and future perspectives. —Jyotika Athavale, Synopsys, USA —Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, France
Authors
- Lukasz G. Szafaryn
- Pradip Bose (ORCID: https://orcid.org/0000-0002-1380-5671)
- Chen-Yong Cher
- Eric Cheng (ORCID: https://orcid.org/0000-0001-8130-2550)
- Subhasish Mitra (ORCID: https://orcid.org/0000-0002-5572-5194)
- Shahrzad Mirkhani
- Hyungmin Cho (ORCID: https://orcid.org/0000-0001-8705-7066)
- Jacob A. Abraham (ORCID: https://orcid.org/0000-0002-5336-5631)
- Mircea R. Stan (ORCID: https://orcid.org/0000-0003-0577-9976)
- K. Lilja
- Kevin Skadron (ORCID: https://orcid.org/0000-0002-8091-9302)
Institutions
- Intel (United States) (US)
- Menlo School (US)
- Robust Chip (United States) (US)
- Fondazione GraphiTech (IT)
- University of Virginia (US)
- Sungkyunkwan University (KR)
- The University of Texas at Austin (US)
- Stanford University (US)
Publication Details
- Journal
- IEEE Design and Test
- Published
- 2024-10-17
- DOI
- https://doi.org/10.1109/mdat.2024.3483028
- Citations
- 3
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 1.47