An 8-bit 5-GS/s Single-Channel Hybrid ADC With a <i>λ</i>/4 Transmission Line Based Time Quantizer

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25~^{\circ }$ </tex-math></inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$ </tex-math></inline-formula>C, and below 0.74 dB over supply variations of ±5%.