Temperature Scaling and <i>C–V</i> Modeling of SiC Low-Voltage MOSFETs for IC Design

A high-temperature (HT) SPICE model of the silicon carbide (SiC) nMOS and pMOS along with the transient characteristics is presented in this article. This work extends the BSIM4SiC model, which primarily addressed the dc characteristics of SiC MOSFETs with a focus on geometry scaling. The BSIM4SiC model has displayed superior accuracy to any other model published for SiC CMOS devices. In this article, the interface trap-related effects on HT performance and capacitance-voltage (C–V) characteristics of the BSIM4SiC model are investigated. The modifications required for model parameters for HT scaling are formulated, while the intrinsic carrier concentration and flat band voltage shift equations are also defined, accounting for the effects of interface traps. A new parameter extraction method for the C–V characteristics was developed for both nMOS and pMOS. The MOSCAP and multifingered MOSFET test structures for the C–V measurements are described. Both the simulated dc and C–V results are matched with the experimental results at high temperatures. The model optimization results of the dc characteristics for different geometries are provided with temperature scaling. The C–V characteristics of the nMOS and pMOS are demonstrated up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~^{\circ }$ </tex-math></inline-formula>C.