Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180[Formula: see text]nm and 90[Formula: see text]nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.