Impact of Trapped Charge on the Breakdown Phenomena in HfO₂/Al₂O₃ — Based Memory Capacitors

Voltage ramp and constant voltage stress (CVS) measurements have been implemented to investigate the breakdown (BD) processes in charge trapping (CT) memory cells with atomic layer deposited (ALD) HfO 2 /Al 2 O 3 nanolaminated stacks. The impact of tunneling oxide thickness as well as post-deposition annealing of memory stacks on the BD characteristics is also studied. The redistribution of the electric field in different parts of the stack due to CT has been calculated and taken into consideration when discussing the BD phenomena. The results imply that there are two BD mechanisms in the charge-trapping stacks — current-driven BD in the high-k part of the stack and voltage-driven BD of the thin tunneling SiO 2 . Each of these mechanisms could dominate depending on the measurement mode (voltage ramp or CVS) and/or trapped charge in the structure. The electric BD is accompanied by a positive charge build-up and generation of interface states at SiO 2 /Si interface. Annealing in O 2 suppresses these processes.