Efficient MAC Unit Design for DSP Processors Using Multiplication and Accumulation Operations

Digital signal processors are essential for intricate processes like filtering and convolution. CPU core integration into a single Integrated Circuit (IC) is widespread to satisfy growing processing needs. Multiply and Accumulate (MAC) units are essential for repeated addition and multiplication in DSP. Performance of the MAC unit has a big impact on the total speed of the DSP algorithm. It is suggested to create a high-speed MAC unit with a pipelined Brent Kung (BK) Adder design and the Vedic multiplier technique. A comparative study with a standard Brent Kung adder and a 32-bit MAC unit reveals that the suggested MAC unit has a speed boost of almost five times. The significance of novel designs, such as the pipelined brent kung Adder architecture and the Vedic multiplier technique, in improving MAC unit performance for digital signal processing applications is highlighted by the synthesis findings. All the designs were implemented on cadence genus EDA tool using Verilog code.