Implementation of FPGA-based ResNet accelerator for vehicle detection

Under the premise of ensuring network performance, ResNet proposes shortcut connections as the basic structure of the network to self-adjust the depth of the network to converge to the identity map. This resolves the performance degradation that occurs after the number of network layers becomes deeper. Field Programmable Gate Array (FPGA) is a highly flexible hardware platform, which is more convenient for the deployment of different neural network structures. Therefore, this paper accelerates ResNet object detection algorithm based on the FPGA platform. Firstly, the ping-pong buffer mechanism ensures data synchronization and correctness in parallel computing, so that the intermediate feature maps are alternately cached within the clock cycle. Secondly, it implements loop unrolling execution of computing tasks at each stage in the pipeline, which made full use of hardware resources and improved computing throughput. In addition, due to the limited resources of FPGA, operator fusion was combined to reduce the power consumption by reducing the number of reads and writes to the cache by the network. Although the accuracy of ResNet acceleration based on the FPGA platform is reduced, the detection speed is increased, and there are certain advantages in performance.