Optimized routing in multi-FPGA systems: a congestion mitigation and TDM allocation approach

Field Programmable Gate Arrays (FPGAs) have attracted widespread attention in the industry due to their high programmability, high-performance computing capabilities, and low power consumption. However, the development of FPGAs has been limited by high transmission latency caused by congestion. In multi-FPGA systems, the number of signals between FPGAs often exceeds the number of I/Os. Time Division Multiplexing (TDM) solves this problem, but an unreasonable TDM allocation scheme can significantly increase latency. In this work, we propose a new routing strategy that consists of three stages: First, we sort the importance of the network. Then, we sequentially perform routing and TDM allocation. Finally, based on the strategies of “Recalculate the path of the highest weight network” and “Adjust other network paths to reduce latency”, we perform rerouting to solve the congestion problem. Based on the System-to-Chip (S2C) problem in the 2023 EDA ICISC and the contest evaluation metric, experimental results show that the routing quality of our framework is 1.31× to 2.04× better than the ordinary situation. This demonstrates the effectiveness of our proposed strategy in improving the performance of FPGA routing. The code is available at https://github.com/sunxiangf/FPGA-Die-Routing.