Design of a high-speed two port SRAM compiler based on advanced technology

This article introduces the design of a high-speed 2-port SRAM compiler based on the 14nm process. In the design process, in order to improve the read and write speed of the circuit, the decoding module was graded for decoding, the storage array was partitioned, and finally, the IO module was redesigned, greatly improving the read and write speed. After the completion of the circuit and layout, post simulation was conducted on the circuit's functions, timing, etc. The simulation voltage was between 0.7 and 1v, the simulation temperature was between -40 and 125 degrees Celsius, and the maximum operating frequency could reach about 2000 MHz, which is about 10% higher than the speed under normal design.