Hybrid series-parallel polynomial multiplier based on Karatsuba algorithm

Polynomial multiplication leads to a significant computational and spatial burden in cryptographic algorithms, posing challenges to optimization endeavors. In this work, we propose a hybrid series-parallel polynomial multiplier based on Karatsuba algorithm. The proposed multiplier can achieve a substantial decrease in the area, while slightly increase the cycle time, thus decrease Area-Delay Product (ADP) greatly, which significantly outperforms the conventional polynomial multiplication algorithms. We implement this architecture on FPGA and achieves the improvement of 32% in area and 49% in ADP compared with conventional algorithm.