An Ultra-Low Power, Low Voltage, Low Line Sensitivity, High PSRR, Voltage Reference for IoT Applications

This paper proposes an all MOSFET transistor-based voltage reference with ultra-low power consumption and high PSRR for Internet of Things applications. The reference voltage is computed using the gate source voltages of the five NMOS transistors, excluding the use of any transistors with high threshold voltages. To provide a steady clamping voltage for the current source, a supply voltage stability circuit with a current source is added which enhances the proposed voltage reference line sensitivity and PSRR. It has been designed and simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology to simulate the proposed voltage reference where all MOSFETs function in the subthreshold region with a 0.5[Formula: see text]V minimum supply voltage. The proposed voltage reference produces a reference voltage of 129.7[Formula: see text]mV with a supply voltage range of 0.5–3[Formula: see text]V. Based on simulation results, the proposed voltage reference has an active area of 0.001[Formula: see text]mm 2 , requires 11.2[Formula: see text]pW of power and has a line sensitivity of 0.021%/V. For a temperature range of [Formula: see text]40 ∘ C to [Formula: see text]C, the circuit achieves a temperature coefficient of 38.2[Formula: see text]ppm/ ∘ C. The power supply rejection ratio of the proposed voltage reference is [Formula: see text]101.5[Formula: see text]dB at 10[Formula: see text]Hz and [Formula: see text]90[Formula: see text]dB at 100[Formula: see text]Hz. The output noise at 100[Formula: see text]Hz and 1[Formula: see text]kHz is 4.68[Formula: see text]and 4.22[Formula: see text][Formula: see text]V/[Formula: see text]Hz, respectively.