Efficient OAM-Based Programmable Hardware Accelerator Architecture

Today, there are a large number of tasks that involve processing data in the form of arrays. These include, in particular, algorithms for fast orthogonal transformations and cryptographic protection of information, whose structure remains consistent regardless of the data. For such algorithms, hardware accelerators are usually used to improve the system performance characteristics. Their architecture traditionally involves an addressable memory, which limits their productivity increase. An efficient programmable hardware accelerator architecture based on conflict-free parallel ordered access memory (OAM) that is based on the corresponding model of computing is proposed in this paper. The approach to OAM-based programmable parallel hardware accelerator design is described and its structure is proposed. The benefits of the proposed programmable hardware accelerator architecture compared to existing conventional architectures are emphasized.