Optimization of Precision and Speed in ADCP

This article introduces a novel principle for the design of interpolating logarithmic Analog-to-Digital Functional Converters (ADFCs) that enhances conversion speed and accuracy. The proposed principle leverages the phenomena of charge redistribution and accumulation during coarse and precise conversion stages, respectively. By simplifying the conversion algorithm and eliminating the need to reproduce previous compensating voltage levels during the coarse conversion stage, the new ADFC design outperforms existing analogs in both speed and precision. The methodological foundations discussed include the selection of conversion steps and the determination of logarithm bases that directly influence the conversion error. The article presents a simplified functional diagram of the ADFC, detailing the operational amplifier’s resistance configuration and the role of capacitive cells in the conversion process. The results demonstrate that the ADFC’s performance can be significantly improved without compromising accuracy, offering advancements in automation, control systems, and information-measurement technology.