A 100-GHz Power Amplifier With 21%/40.5% 1-/3-dB FBW and 15.1-dBm P<sub>SAT</sub> Using Pole-Tuning Interstage Matching Network in 65-nm CMOS
This letter presents a wideband two-way current-combining power amplifier (PA) for sub-terahertz (sub-THz) wireless communication. The transformer-based fourth-order pole-tuning interstage matching network (IMN) is proposed, analyzed, and adopted to feature flat in-band frequency responses. Fabricated in 65-nm CMOS technology, the PA chip achieves a 1-/3-dB bandwidth of 21.0/40.2 GHz (90.0–111.0/81.1–121.3 GHz) with 21.0%/40.5% 1-/3-dB fractional bandwidth, 15.1-dBm saturated output power, and a peak power-added efficiency (PAE) of 17.1% at 114 GHz. The core chip area of the proposed PA is only 0.12 mm2, leading to a power density of 269.7 mW/mm2.
Authors
- Yiting Zhang (ORCID: https://orcid.org/0000-0001-7491-2895)
- Zhen Yang (ORCID: https://orcid.org/0000-0002-0005-6261)
- Nengxu Zhu (ORCID: https://orcid.org/0000-0002-5925-1838)
- Fanyi Meng (ORCID: https://orcid.org/0000-0003-0989-3119)
Institutions
- Tianjin University (CN)
Publication Details
- Journal
- IEEE Microwave and Wireless Technology Letters
- Published
- 2024-10-16
- DOI
- https://doi.org/10.1109/lmwt.2024.3473932
- Citations
- 2
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.42
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China