A capacitor-free CMOS low-dropout regulator with gate-coupled flipped voltage follower for SOC

This paper proposes a fully integrated low dropout (LDO) regulator with gate-coupled flipped voltage follower(GC-FVF). The proposed GC-FVF addresses the limited output swing issue of conventional PMOS FVF in LDOs while maintaining a low output impedance. Besides, this LDO introduces a cascode compensation loop, which, along with the low output impedance of GC-FVF, pushes the output pole far away from the unity-gain bandwidth under both light and heavy load conditions. Consequently, the LDO becomes a stable two-pole system, supporting a high loop gain of up to 100dB and significantly enhancing the load and line regulation. Key specifications include a preset output voltage of 1.8V, a minimum unregulated input voltage of 2V, a maximum output current of 100mA, a ground current of 32μA, and an active chip area of 260μm×180μm.