Mitigation of Hardware Trojan in NoC using Delta-Based Compression

MultiProcessor System-on-Chip (MPSoC) and Network-on-Chip (NoC) are closely linked in the design of modern computer architectures. Indeed, MPSoCs are designed to integrate multiple processing units on a single chip and take advantage of NoCs to suppport communications between these multiple processors. As data exchanges via the NoC can be voluminous, it can lead to increased latency and bandwidth consumption. Thus, on-chip packet compression techniques exploiting data correlation may mitigate these issues. However, compression can make data more sensitive to faults or attacks. Therefore, it is important to consider the potential presence of hardware Trojans (HT) within some of the intellectual properties (IP) embedded in the NoC. In this article, we focus on Delta-based compression, which allows the compression of a set of data using one base and distances. After formalizing the delta-based compression cost, we analyze the impact of fault injection attacks on application quality degradation. Additionally, we present a lightweight mitigation technique focusing on bases protection by using freely available bits in the header flit. Experiments show that our mitigation technique is effective in reducing the impact of hardware Trojan attacks on compressed packet data with a mean squared error gain up to 67% and a loss in compression ratio of around 8% for CIFAR-10 database.