A 20-kHz 106.1-dB SNDR Σ–Δ DAC Using FIA With Dynamic-Body-Biasing-Assisted CLS Technique

This article proposes a low-power noise-shaping digital-to-analog converter (DAC) that utilizes a floating inverter amplifier (FIA) and dynamic-body-biasing assisted correlated level shifting (CLS) technology in the switched capacitor DAC to reduce power consumption and enhance gain. Based on the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma $ </tex-math></inline-formula>-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula> DAC structure, this DAC consists of interpolation filters, a 4th-order cascade of integrators feed-forward (CIFB) modulator with 4-bit quantization, and an improved switched capacitor DAC. The data-weighted averaging (DWA) algorithm circuit is employed to minimize the impact of capacitor mismatch. Fabricated in a 180nm CMOS process, the layout occupies 0.45 mm2. The switched capacitor DAC achieves a maximum SNDR of 106.1 dB over a 20 kHz bandwidth and consumes only 1.82 mW from a 3.3 V supply when the sampling frequency (fs) is set to be 12.288 MS/s. Compared to traditional architectures, this structure successfully reduces the circuit power consumption from 3.87mW to 1.82mW by using FIA dynamic amplifiers, optimizing power consumption by approximately 53%. Additionally, to enhance integration accuracy, CLS technology is employed to increase the equivalent gain of the FIA amplifiers by at least 30dB.