AMBEATion: New Algorithm for Generation IC Matched Structures with Respecting Linear and Non-linear Gradient Parameter Effects

This paper presents an innovative algorithm designed by AMBEATion consortium for optimizing the position of the critical structures in semiconductor integrated circuits (IC). The consortium, includes global semiconductor companies and leading universities, aims to address this challenge. The algorithm showcased its efficacy through testing on 6 600 diverse cases, particularly focusing on the 3rd order of the non-linear gradient of the environment. The results reveal high-quality matched performance, exemplified by minimal threshold voltage mismatches for current mirrors. The algorithm’s versatility makes it a recommended solution for varied applications. It emphasizes the need for configuring control parameters efficiently within the modified Simulated Annealing (SA) methodology, highlighting its significance in achieving optimal computational efficiency and performance across different technological domains.