Bottom-Gate Poly-Si Thin Film Transistors Fabricated by Blue Laser Diode Annealing and Their Reliability Under DC and AC Bias Stresses

We investigate the electrical reliability of inverted staggered low-temperature poly-Si (LTPS) thin-film transistors (TFT) under direct and alternate current (DC and AC gate pulses) operations fabricated by blue laser diode annealing (BLDA). From scanning electron microscopy (SEM), and atomic force microscopy (AFM) images, smaller grain sizes (~70 nm) and smoother poly-Si surface (~1.18 nm) are achieved for solid-phase crystallization (SPC) by BLDA crystallization. However, partial melting (PM) of the silicon active layer exhibits a large grain size (~200 nm) with comparatively taller surface roughness (~7.73 nm). As compared to SPC devices, PM devices exhibit more electrical degradation including drain current (I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {DS}}\text {)}$ </tex-math></inline-formula> instability and threshold voltage shift (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>V<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {Th}}\text {)}$ </tex-math></inline-formula> under AC stress. Although, PM TFTs exhibit higher IDS, and field-effect mobility (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}\text {)}$ </tex-math></inline-formula>, the protruded poly-Si layer causes severe carrier trapping/detrapping at grain boundary (GB) under AC stress. Besides, both the devices show stable electrical behavior under negative bias temperature stress (NBTS). We performed the technology computer-aided design (TCAD) simulation to validate the physical mechanism.