Investigating the Tapered Profiles on the Parasitic Inductance of Through-Silicon Vias
In this study, we extract S-parameters from a ground-signal–ground (GSG)-type tapered through-silicon via (TSV) model within the frequency range of 20–40 GHz and subsequently convert them into the resistance, inductance, conductance, and capacitance (RLGC) electrical model. We analyze the impact of tapers on TSV inductance and develop a comprehensive formulation to rigorously account for the parasitic inductance of tapered TSVs in high-density 3-D integration, based on geometrical parameters. Furthermore, we explore the correlation between the pitch of vias and the composition of the TSV’s parasitic inductance.
Authors
- Tianpeng Liang (ORCID: https://orcid.org/0000-0002-5702-4332)
- Wenlei Li (ORCID: https://orcid.org/0000-0002-2310-9872)
- Jinxu Liu (ORCID: https://orcid.org/0000-0003-4028-8670)
- Libin Gao (ORCID: https://orcid.org/0000-0001-8198-9014)
- Hongwei Chen (ORCID: https://orcid.org/0000-0002-4700-0767)
- Zhen Fang (ORCID: https://orcid.org/0000-0001-8482-8013)
- Wanli Zhang (ORCID: https://orcid.org/0000-0002-7513-2185)
- Jihua Zhang (ORCID: https://orcid.org/0000-0003-3136-1194)
Institutions
- University of Electronic Science and Technology of China (CN)
- Chengdu University of Technology (CN)
- National Engineering Research Center of Electromagnetic Radiation Control Materials (CN)
Publication Details
- Journal
- IEEE Transactions on Components Packaging and Manufacturing Technology
- Published
- 2024-10-14
- DOI
- https://doi.org/10.1109/tcpmt.2024.3480697
- Citations
- 1
- Primary Topic
- Semiconductor materials and interfaces
- Type
- article
- Field-Weighted Citation Impact
- 0.34