Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al₂O₃ gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al 2 O 3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm 2 /(V∙s), a subthreshold swing of 136 mV dec −1 , and an on-/off-current ratio above 10 9 . PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 10 9 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.