Design and Implementation of Low Power 1 and 2 Trit Multipliers

Multipliers are combinational logic circuits used in applications like computers, calculators, general-purpose processors and digital signal processors. They are widely used in a variety of signal-processing applications, as 70% of these applications use algorithms which include addition and multiplication operations. In VLSI/embedded applications, power consumption is an important factor to lessen the cost of the chip and enhance battery life. Traditional multipliers are implemented using binary logic, in which each line carries two signal levels, logic 0 or logic 1. In contrast, Ternary logic uses circuits, which carry three levels 0,1, and 2, known as trits. Ternary gates, which are required for ternary multipliers, are implemented using multi-threshold MOSFETs. Leakage current and, hence, static power can be reduced by a forced stack that deploys additional transistors to split the current. In this paper, low-power ternary gates are realized using the forced stack technique. This work mainly designs and implements 1-trit and 2-trit multipliers utilizing low-power ternary logic gates, using Cadence Virtuoso using 45nm Technology. The power of the 1-trit multiplier and 2-trit multiplier is compared with that of its counter binary multipliers, which show reduced power consumption. Further, this work proposes a novel technique to implement a ternary multiplier using Single Pole Triple Throw (SPTT) switches, resulting in a reduced number of transistors.