Processing techniques for metrological improvement of low-cost smart meter hardware solution for IEC 61000-4-7 Class I harmonics measurements

• An experimental study is presented on the feasibility of using low-cost microcontroller boards for harmonics measurements according to IEC 61000-4-7 Class I requirements. • To improve the measurement accuracy, time domain interpolation algorithms (Farrow and Lagrange polynomial) are analyzed and compared both in simulation and in experimental tests. • Interpolation and FFT algorithms are implemented in a case study microcontroller device, and different sampling and processing solutions are compared in terms of measurement accuracy, computational cost, and memory requirements in order to increase metrological ADC behavior. • The microcontroller device performances are compared with those of a more accurate PC-based instrument and errors on harmonic analysis obtained with the different solutions are compared with the IEC 61000-4-7 Class I limits. • The feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements has been verified. The work investigates the feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements. The final aim was to evaluate to what extent Class I harmonic analysis can be integrated into existing low-cost hardware platforms for smart metering, which normally have limited hardware features, especially concerning the ADC and the possibility of varying the sampling frequency with high resolution, according to the power system signal frequency. An extended experimental characterization is carried out on a case study device, aimed at analyzing its performances in terms of both measurement accuracy and computational burden. To increase metrological ADC behavior and decrease computational costs, sampling strategies and optimized interpolation algorithm have been implemented and tested verifying the feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements.

Authors

Institutions

Publication Details

Journal
Measurement
Published
2024-10-12
DOI
https://doi.org/10.1016/j.measurement.2024.115898
Citations
3
Primary Topic
Advanced Electrical Measurement Techniques
Type
article
Field-Weighted Citation Impact
0.63

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Processing techniques for metrological improvement of low-cost smart meter hardware solution for IEC 61000-4-7 Class I harmonics measurements

Salvatore Guaiana, Nicola Panzavecchia, Lionel Cimaz, Antonio Cataliotti et al.
3 citations
Measurement
Advanced Electrical Measurement Techniques
0.63
article

Processing techniques for metrological improvement of low-cost smart meter hardware solution for IEC 61000-4-7 Class I harmonics measurements

Salvatore Guaiana, Nicola Panzavecchia, Lionel Cimaz, Antonio Cataliotti, Dario Di Cara, Valentina Cosentino, Vito Ditta, Marilena G. Sambataro, Nunzio Dipaola, Giovanni Artale, Giovanni Tinè
article en
3 citations

Abstract

• An experimental study is presented on the feasibility of using low-cost microcontroller boards for harmonics measurements according to IEC 61000-4-7 Class I requirements. • To improve the measurement accuracy, time domain interpolation algorithms (Farrow and Lagrange polynomial) are analyzed and compared both in simulation and in experimental tests. • Interpolation and FFT algorithms are implemented in a case study microcontroller device, and different sampling and processing solutions are compared in terms of measurement accuracy, computational cost, and memory requirements in order to increase metrological ADC behavior. • The microcontroller device performances are compared with those of a more accurate PC-based instrument and errors on harmonic analysis obtained with the different solutions are compared with the IEC 61000-4-7 Class I limits. • The feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements has been verified. The work investigates the feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements. The final aim was to evaluate to what extent Class I harmonic analysis can be integrated into existing low-cost hardware platforms for smart metering, which normally have limited hardware features, especially concerning the ADC and the possibility of varying the sampling frequency with high resolution, according to the power system signal frequency. An extended experimental characterization is carried out on a case study device, aimed at analyzing its performances in terms of both measurement accuracy and computational burden. To increase metrological ADC behavior and decrease computational costs, sampling strategies and optimized interpolation algorithm have been implemented and tested verifying the feasibility of harmonic analysis implementation on smart meter microcontroller devices, according to IEC 61000-4-30 Class A and IEC 61000-4-7 Class I requirements.

MeasurementVol. 242
STMicroelectronics (Switzerland) (CH), STMicroelectronics (France) (FR), Institute of Marine Engineering (IT), National Research Council (IT), University of Palermo (IT)
European Commission, Consiglio Nazionale delle Ricerche, Università degli Studi di Palermo
Openalex Percentile: Top 31%
Advanced Electrical Measurement Techniques
0.63
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.