A 12/24 V-to-Sub-1 V Double Step-Down Converter With Dual-Ramp Control for <i>V</i> _CF Balancing and Fast Transient Response

In the data centers and artificial intelligence supercomputers, power supplies are urgently needed to offer high conversion ratio with high efficiency and fast transient response. Current solutions struggle to achieve both high efficiency and fast transient response, simultaneously. This article introduces a novel double step-down (DSD) converter featuring a dual-phase ramp for 12/24 V-to-sub-1 V conversion. The impact of flying capacitor voltage <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CF</sub> deviation on DSD converters is analyzed and a dual-ramp control architecture is proposed to alleviate <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CF</sub> deviation, thereby enhancing the system's robustness. Additionally, we propose a novel approach of leveraging high-frequency pulse injection to suppress undershoot and introduce a discharge path to mitigate overshoot; thereby, the transient characteristics of the converter are significantly improved. By seamlessly integrating low-frequency steady-state control with high-frequency transient enhancement control, this work successfully overcomes the conventional bottleneck of balancing high efficiency and fast transient response. The most distinctive feature is that the proposed dual-ramp and transient enhancement synergy achieves <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CF</sub> balancing during both steady-state and transient responses. A prototype is implemented with a 0.18-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i>m bipolar-CMOS-DMOS technology, achieving high power efficiencies of 92.2%, 89.1%, and 83% at frequencies of 250 kHz, 500 kHz, and 1 MHz, respectively. During a load transient of 1.49 A/300 ns, the undershoot and overshoot are reduced to 280 mV and 160 mV, respectively, and the corresponding response times are 20 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i>s and 12 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i>s, respectively. Measurement results highlight the synchronous enhancement in both efficiency and transient response achieved by the proposed method and topology.