Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs

Delivering an FPGA-based emulation model to the software and hardware development teams is one of the crucial steps in the chip design process. The parallelism available on the FPGA gives a performance boost necessary to speed up development and verification processes and benefits both hardware and software engineers. However, this step is challenging in the asynchronous circuits design flow due to the limitations of the commercially available FPGA platforms and electronic design automation (EDA) tools. We present a comprehensive solution to the problem of asynchronous design emulation on synchronous FPGAs by extending prior work for emulating gate-level asynchronous designs (Hoare, 1978). Our framework supports asynchronous designs described at the behavioral level in the communicating hardware processes language, the gate level, and hybrid designs that combine the two. We also support designs where parts of the system use natively synchronous logic. We show that our model for behavioral emulation is up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 10^{5}$ </tex-math></inline-formula> faster than CPU-based simulation and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.96\times $ </tex-math></inline-formula> faster than the gate-level emulation model of the same design. We evaluate our toolchain using three real-world asynchronous design examples. We present a case study where we use our flow to emulate an asynchronous CPU on the synchronous FPGA and use this hardware to boot a real-time operating system, Zephyr RTOS. In this example, FPGA I/O interfaces use synchronous Verilog IP, and the RISC-V core model is generated from the asynchronous design.