A lightweight reconfigurable hardware accelerator for depthwise separable convolution

Convolutional Neural Networks (CNNs) have witnessed increasingly widespread applications in the field of computer vision with the development of artificial intelligence. The Depthwise Separable Convolutional Neural Network, owing to its characteristics such as fewer parameters, high computational efficiency, and good generalization capabilities, holds significant advantages for deployment on resource-constrained embedded terminals. Presently, numerous accelerator solutions focus on accelerating larger network models like VGG and ResNet. However, when running Depthwise Separable Convolutional Neural Networks on these accelerators, issues such as slow execution speed and low utilization of computational resources persist. In this study,we adopts the advanced Deep Separable Convolutional Neural Network, ShuffleNetV2, as the foundational architecture for investigation. A novel hardware optimization approach is proposed for the implementation of standard convolution and depthwise convolution, aiming to enhance the utilization efficiency of hardware computational resources. The proposed hardware accelerator is implemented on Xilinx xczu9eg FPGA at a clock frequency of 150 MHz, achieves a maximum frame rate of 675.7 fps. Simultaneously, it exhibits a power consumption of only 7.3 W, resulting in a power efficiency of 13.45 GOPS/W. In comparison to GPU platforms, the proposed design demonstrates a 12% improvement in execution speed, while simultaneously achieving a power efficiency that is 20.4 times than that of GPU platform. Compared to similar hardware accelerators proposed in recent years, the resource consumption of this design is comparatively smaller, and it holds a certain advantage in terms of speed and power consumption.