A 10-b 500KS/s low-power SAR ADC for smart sensing in 40nm CMOS

Low-power signal acquisition is critical in smart sensing applications, such as multi-channel EEG systems. SAR ADC is a perfect candidate for power-efficient A/D conversion because of its amplifier-free structure. This paper presents the circuit design of a 10-bit low-power SAR ADC for biomedical signal acquisition. Synchronous SAR logic is adopted for its robustness, and a fully dynamic comparator is utilized to reduce ADC power consumption. Unit capacitance is designed to 10fF in this ADC to guarantee the DAC matching requirement. The transistor-level simulation results of the SAR ADC in 40nm CMOS show that with a 500KS/s sampling frequency and a Nyquist input frequency, the designed ADC achieves an SNDR of 61.04dB and an SFDR of 70.41dB. The power consumption of the SAR ADC is only 9.36μW, corresponding to a state-of-the-art FoM of 20.28fJ/conv-step.