Formalization of topology and electrical circuit verification for computer-aided design systems

The article examines the study of methods for verifying the correspondence of topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of the topological structure, taking into ac-count electrical characteristics, which leads to an increase in the formalization of tasks and provides better optimization of human interaction and a computer CAD system. The research includes an analysis of modern methods and tools used in the development of electronic devices, and also offers innovative approaches to ensuring consistency between to-pology and electrical functionality. LVS verification of the project is performed using Calibre, xRC extraction of the project, physical verification of the project using CADENCE Physical Verification System (PVS), LVS verification of the project using PVS. Presents a detailed analysis of the inte-grated circuit verification process performed using modern CAD tools. The paper discusses the key stages of verifica-tion, including LVS verification of the project using the Cal-ibre tool, xRC extraction of the project, as well as physical verification of the project using Cadence Physical Verifica-tion System (PVS). Special attention is paid to LVS checks, which represent an important design stage that guarantees the compliance of the topology and the electrical circuit. The features of using Calibre to perform LVS checks, as well as the xRC extraction process to extract the parameters of re-sistors and capacitors, are considered. For the physical veri-fication of the project, the capabilities of Cadence PVS were used, which provides an analysis of the compliance of the physical implementation of the scheme with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers in-volved in the design of integrated circuits, as well as for those interested in the use of modern CAD tools in the field of verification and validation of electronic devices

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Publication Details

Journal
Modeling of systems and processes
Published
2024-10-01
DOI
https://doi.org/10.12737/2219-0767-2024-59-68
Citations
30
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
14.67
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article

Formalization of topology and electrical circuit verification for computer-aided design systems

Konstantin Zolnikov, Aleksey Plotnikov, I Scorkin, Tatyana Skvortsova
30 citations
Modeling of systems and processes
Embedded Systems Design Techniques
14.67
article

Formalization of topology and electrical circuit verification for computer-aided design systems

Konstantin Zolnikov, Aleksey Plotnikov, I Scorkin, Tatyana Skvortsova
article en
30 citations

Abstract

The article examines the study of methods for verifying the correspondence of topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of the topological structure, taking into ac-count electrical characteristics, which leads to an increase in the formalization of tasks and provides better optimization of human interaction and a computer CAD system. The research includes an analysis of modern methods and tools used in the development of electronic devices, and also offers innovative approaches to ensuring consistency between to-pology and electrical functionality. LVS verification of the project is performed using Calibre, xRC extraction of the project, physical verification of the project using CADENCE Physical Verification System (PVS), LVS verification of the project using PVS. Presents a detailed analysis of the inte-grated circuit verification process performed using modern CAD tools. The paper discusses the key stages of verifica-tion, including LVS verification of the project using the Cal-ibre tool, xRC extraction of the project, as well as physical verification of the project using Cadence Physical Verifica-tion System (PVS). Special attention is paid to LVS checks, which represent an important design stage that guarantees the compliance of the topology and the electrical circuit. The features of using Calibre to perform LVS checks, as well as the xRC extraction process to extract the parameters of re-sistors and capacitors, are considered. For the physical veri-fication of the project, the capabilities of Cadence PVS were used, which provides an analysis of the compliance of the physical implementation of the scheme with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers in-volved in the design of integrated circuits, as well as for those interested in the use of modern CAD tools in the field of verification and validation of electronic devices

Modeling of systems and processes
Voronezh State University of Forestry and Technologies (RU)
Industry, innovation and infrastructure
Openalex Percentile: Top 0%
Embedded Systems Design Techniques
14.67
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