Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

ABSTRACT Designing FFTs with higher radix butterfly units are increasingly in demand to combat the high throughput of 20 Gbps of the current 5G and 1 Tbps for beyond 5G technologies. Previous higher radix FFTs were implemented in FPGA, giving importance to area and power. This paper presents the design of radix‐power‐of‐2 butterfly circuit, using the proposed radix cosine coefficients' extractor equation that is applicable to all the inputs. This enables efficient pipelined shift‐add implementation of the required complex rotations. The proposed methodology encompasses the implementation of any power‐of‐two‐radix butterfly to realize large size FFT, essential for real‐time 5G and 6G applications. The proposed radix‐4, radix‐8, radix‐16, and radix‐32 architectures are implemented and verified on Xilinx Spartan‐7 FPGA using Vivado Design Suite (v2018). The results demonstrate that the proposed radix‐16 and radix‐32 architectures achieve a higher clock frequency, by a factor of 5.23 and 6.76, respectively, compared to the most recent literature. For performance analysis, the area‐delay and power‐delay products of the proposed radix‐16 and radix‐32 butterfly architecture are computed. The proposed radix‐16 butterfly architecture exhibits a 13.3% reduction in area‐delay product and a 34.25% decrease in power‐delay product compared to recent literatures. Similarly, the radix‐32 architecture shows a 27.31% lower area‐delay product and a 0.63% lower power‐delay product.