A 10.7‐μA 103‐dB DR Hybrid Delta‐Sigma Modulator for Sensing Applications

ABSTRACT This paper reports a low‐power, high dynamic range second‐order delta‐sigma modulator (DSM) for sensing applications. The DSM employs a hybrid CIFF‐B topology, consisting of a continuous‐time first stage and a discrete‐time second stage. The first stage is an OTA‐based RC integrator with inherent anti‐aliasing properties, while the second stage is a switched‐capacitor integrator. Offset and noise in the first stage are mitigated by the chopper‐stabilization technique, while those in the second stage are suppressed through the gain provided by the first stage. Furthermore, the OTA‐sharing technology is utilized in the second stage to realize signal addition before quantization, reducing design complexity. The hybrid DSM prototype is fabricated with a 180‐nm CMOS process and occupies an area of 0.123 mm 2 . Measurement results show peak SNDR/SNR/SFDR values of 95.8, 97.1, and 102.8 dB, respectively, with a current consumption of 10.7 A from a 1.8‐V single supply. The reported DSM achieves a 103‐dB dynamic range in a 100‐Hz signal bandwidth, corresponding to a Schreier figure‐of‐merit (FoMs) value of 170.2 dB.