Impact on Delay, Power and Area of Machine Learning-based Approximate Logic Synthesis

Logical optimization is a crucial step in circuit synthesis, directly impacting the design’s area, power, and delay metrics. Machine Learning techniques are particularly suitable for approximate logic synthesis and optimization in error-resilient scenarios. This work investigates the impact of using ML techniques for logic optimization and enhancing energy efficiency in approximate circuit synthesis. We consider three state-of-the-art approximate logic optimization approaches based on mixed-ML, Decision Trees (DT), and Cartesian Genetic Programming (CGP). This work presents a comparative analysis of physical synthesis results for a set of approximate circuit benchmarks, using an open synthesis flow and a 45 nm technology standard cell library. From the techniques evaluated, CGP-based logical optimization shows a reduction in area, power, and delay of more than 50% on average compared to the mixed-ML approach. However, this improvement was accompanied by an average accuracy loss of about 5%. These findings highlight the substantial potential of the CGP approach in optimizing approximate circuits.