A 9.78-ENOB 10 MS/s SAR ADC with a Common Mode Compensation Technique in a 28nm CMOS Node

A 10-bit differential synchronous SAR ADC designed in 28 nm CMOS technology is proposed for integration into a system-on-chip (SoC). The implemented DAC employs monotonic switching to reduce settling time and power consumption by minimizing capacitance. Additionally, a novel technique is introduced to eliminate common-mode voltage drop in capacitors corresponding to the 3 most significant bits. Simulated post-layout testing demonstrates a typical effective number of bits (ENOB) of 9.78 at maximum sampling frequency for Nyquist frequency input, with a power consumption of 489.7 µW. Static tests reveal a differential non-linearity (DNL) of +0.16/-0.23 LSB and an integral non-linearity (INL) of ±0.4 LSB. The figure of merit (FoM) is calculated as 55.82 fJ/Conv.