Layout Design of an Asynchronous Time-Based Image Sensor with Shared DVS Module

In the asynchronous time-based image sensor (ATIS), capture is performed asynchronously by each pixel when the dynamic vision sensor (DVS) module detects significant luminance change. The DVS module control aims at avoiding redundant capture. Furthermore, time-based capture allows for high dynamic range imaging. Each original ATIS pixel is composed by a capture module and a DVS module, resulting in a large pixel area and small fill factor. DVS module sharing reduces the pixel area and increases the fill factor. In this work, we present simulation results and layout design of an ATIS in which each 2×2 capture modules share a single DVS module. Corners, Monte Carlo, and post-layout simulations are presented. With the layout, designed in a 180 nm complementary metal-oxide semiconductor (CMOS) technology, we conclude that the DVS sharing saves approximately 33.68% area and the pixel fill factor is 7.7%. Simulation results indicate that the circuit operation is robust to fabrication errors and to layout parasitic components.