Fast and Practical Strassen’s Matrix Multiplication using FPGAs

Matrix multiplication is a cornerstone operation in a wide array of scientific fields, including machine learning and computer graphics. The standard algorithm for matrix multiplication has a complexity of $O\left(n^{3}\right)$ for $n \times n$ matrices. Strassen’s algorithm improves this to $O\left(n^{2.807}\right)$, but its practicality is limited for small to medium matrix sizes due to the large number of additions it introduces. This paper presents a novel FPGA-based implementation of Strassen’s algorithm that achieves superior speed over an optimized General Matrix Multiply (GeMM) implementation for matrices as small as n = 256. Our design, tested extensively on two high-performance FPGA accelerators (Alveo U50 and U280) across various data types, matches or surpasses the performance of a highly optimized baseline across a range of matrix sizes.

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Publication Details

Published
2024-09-02
DOI
https://doi.org/10.1109/fpl64840.2024.00050
Citations
1
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.21
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Fast and Practical Strassen’s Matrix Multiplication using FPGAs

Wei Zhang, Afzal Ahmad, Linfeng Du
1 citations
VLSI and FPGA Design Techniques
0.21
article

Fast and Practical Strassen’s Matrix Multiplication using FPGAs

Wei Zhang, Afzal Ahmad, Linfeng Du
article en
1 citations

Abstract

Matrix multiplication is a cornerstone operation in a wide array of scientific fields, including machine learning and computer graphics. The standard algorithm for matrix multiplication has a complexity of $O\left(n^{3}\right)$ for $n \times n$ matrices. Strassen’s algorithm improves this to $O\left(n^{2.807}\right)$, but its practicality is limited for small to medium matrix sizes due to the large number of additions it introduces. This paper presents a novel FPGA-based implementation of Strassen’s algorithm that achieves superior speed over an optimized General Matrix Multiply (GeMM) implementation for matrices as small as n = 256. Our design, tested extensively on two high-performance FPGA accelerators (Alveo U50 and U280) across various data types, matches or surpasses the performance of a highly optimized baseline across a range of matrix sizes.

Hong Kong University of Science and Technology (HK)
Openalex Percentile: Top 47%
VLSI and FPGA Design Techniques
0.21
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