Energy-Aware Synchronization of Hardware Tasks in Virtualized Embedded Systems

Dynamic Voltage and Frequency Scaling (DVFS) is an effective means to reduce the energy dissipation of digital designs. While on most commodity FPGAs, memory and processor have separately controlled voltages, the programmable logic section relies on a single voltage rail and thus imposes the same voltage for all hardware accelerators that operate concurrently. Finding time slots eligible for voltage scaling gets difficult in virtualized systems, where the FPGA is shared by tasks executed in multiple guest operating systems. The situation gets even more complicated, when error-tolerant tasks are considered that allow the voltage to be reduced below its nominal value, which could provoke a certain rate of faulty hardware accelerator runs. As a solution, we propose a strategy that synchronizes concurrently executed periodic hardware tasks under consideration of their reliability as well as their real-time requirements so that the supply voltage is controlled accordingly. The proposed strategy can be combined with further mechanisms for saving energy. Our run-time module performs clock gating and adjusts the voltage to the requirements of aperiodic tasks. For fault-tolerant tasks, we monitor the error rate using Algorithm Based Fault Tolerance (ABFT) that can detect and characterize errors with an accuracy close to $100 \%$. Compared to a strategy that scales voltage without synchronizing hardware tasks, we achieve in the best case a power saving by $29.4 \%$ and an average saving by $7 \%$.